SAT-based equivalence checking of threshold logic designs for nanotechnologies

Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metal-oxide semiconductor (CMOS) technology in future circuit design. However, many nanotechnologies are intrinsically suitable for implementing threshold logic rather than Boolean logic which has dominated CMOS technology in the past. To fully take advantage of such emerging nanotechnologies, efficient design automation tools for threshold logic therefore become essential. In this work, we propose novel techniques of formulating a given threshold logic in conjunctive normal form (CNF) that facilitates efficient SAT-based equivalence checking. Three different strategies of CNF generation from threshold logic representations are implemented. Experimental results based on MCNC benchmarks are presented as a complete comparison. Our hybrid algorithm, which takes into account input symmetry as well as input weight order of threshold gates, can efficiently generate CNF formulas in terms of both SAT solving time and CNF generating time.