Design and Analysis of Dynamic Redundancy Networks

The dynamic redundancy (DR) network is investigated in relation to fault-tolerant design for multistage interconnection network (MIN) based systems. The DR network can tolerate faults in the network and support a system to tolerate processing element (PE) faults without degradation by adding spare PEs, while retaining the full capability of a multistage cube network. A variation of the DR network, the reduced DR network, is also considered, that can be implemented more cost effectively than the DR while retaining most of the advantages of the DR. The reliabilities of DR-based systems with one spare PE and the reliabilities of systems with no spare PEs are estimated and compared, and the effect of adding multiple spare PEs is analyzed. >

[1]  Duncan H. Lawrie,et al.  Fault Tolerance Schemes in Shuffle-Exchange Type Interconnection Networks , 1983, ICPP.

[2]  Nian-Feng Tzeng,et al.  Fault-Tolerant Scheme for Multistage Interconnection Networks , 1985, ISCA.

[3]  Dharma P. Agrawal,et al.  A Survey and Comparision of Fault-Tolerant Multistage Interconnection Networks , 1987, Computer.

[4]  Jack B. Dennis,et al.  Building blocks for data flow prototypes , 1980, ISCA '80.

[5]  Howard Jay Siegel,et al.  Modifications to improve the fault tolerance of the extra stage cube interconnection network , 1984 .

[6]  Ralph Grishman,et al.  The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer , 1983, IEEE Transactions on Computers.

[7]  V. P. Kumar,et al.  Design and analysis of fault-tolerant multistage interconnection networks with low link complexity , 1985, ISCA 1985.

[8]  Robert S. Swarz,et al.  The theory and practice of reliable system design , 1982 .

[9]  Howard Jay Siegel,et al.  The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems , 1982, IEEE Transactions on Computers.

[10]  Tse-Yun Feng,et al.  Star: A Local Network System for Real-Time Management of Imagery Data , 1982, IEEE Transactions on Computers.

[11]  Mark A. Franklin,et al.  VLSI Performance Comparison of Banyan and Crossbar Communications Networks , 1981, IEEE Transactions on Computers.

[12]  Suchai Thanawastien,et al.  Interference Analysis of Shuffle/Exchange Networks , 1981, IEEE Transactions on Computers.

[13]  Tse-Yun Feng,et al.  Fault Diagnosis of Multistage Interconnection Networks with Four Valid States , 1985, ICDCS.

[14]  Pen-Chung Yew,et al.  A fault tolerant interconnection network using error correcting codes , 1982, ICPP.

[15]  Howard Jay Siegel,et al.  Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.) , 1985 .

[16]  Robert J. McMillen,et al.  Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network , 1982, ISCA '82.

[17]  Robert J. McMillen,et al.  Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network , 1982, ISCA 1982.

[18]  Kang G. Shin,et al.  Analysis of the impact of error detection on computer performance , 1983 .

[19]  Kenneth E. Batcher,et al.  The flip network in staran , 1976 .

[20]  Robert H. Thomas,et al.  Performance Measurements on a 128-Node Butterfly Parallel Processor , 1985, ICPP.

[21]  Stephen F. Lundstrom,et al.  Design and Validation of a Connection Network for Many-Processor Multiprocessor Systems , 1981, Computer.

[22]  D. P. Agarwal,et al.  Fault tolerant capabilities of redundant multistage interconnection networks (multiprocessors) , 1983 .

[23]  Monty Denneau,et al.  The GF11 supercomputer , 1985, ISCA '85.

[24]  Robert J. McMillen,et al.  The Multistage Cube: A Versatile Interconnection Network , 1981, Computer.

[25]  Howard Jay Siegel,et al.  Fault location techniques for distributed control interconnection networks , 1985, IEEE Transactions on Computers.

[26]  Howard Jay Siegel The Theory Underlying the Partitioning of Permutation Networks , 1980, IEEE Transactions on Computers.

[27]  Luigi Ciminiera,et al.  A fault-tolerant connecting network for multiprocessing systems , 1982, ICPP.

[28]  Marshall C. Pease,et al.  The Indirect Binary n-Cube Microprocessor Array , 1977, IEEE Transactions on Computers.

[29]  Kevin P. McAuliffe,et al.  The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture , 1985, ICPP.

[30]  Duncan H. Lawrie,et al.  A Class of Redundant Path Multistage Interconnection Networks , 1983, IEEE Transactions on Computers.

[31]  Michael J. Flynn,et al.  Very high-speed computing systems , 1966 .

[32]  Howard Jay Siegel,et al.  Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks , 1977, IEEE Transactions on Computers.

[33]  William C. McDonald,et al.  The Advanced Data Processing Testbed , 1978, COMPSAC.

[34]  Daniel M. Dias,et al.  Augmented and pruned n log n multistaged networks: topology and performance , 1982, ICPP.

[35]  Robert J. McMillen,et al.  Evaluation of cube and data manipulator networks , 1985, J. Parallel Distributed Comput..

[36]  John P. Hayes,et al.  Fault tolerance of a class of connecting networks , 1980, ISCA '80.

[37]  Howard Jay Siegel,et al.  PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition , 1981, IEEE Transactions on Computers.

[38]  Tse-Yun Feng,et al.  On a Class of Multistage Interconnection Networks , 1980, IEEE Transactions on Computers.

[39]  Chin-Tau A. Lea,et al.  The Load-Sharing Banyan Network , 1986, IEEE Transactions on Computers.

[40]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.