Incremental routing algorithms for fpgas and vlsi circuits

Incremental routing is a crucial phase in incorporating late design changes in complex circuits to correct problems such as timing violations, crosstalk and temperature hot-spots that are often seen in current very deep submicron (VDSM) chips. This dissertation presents novel incremental routing algorithms DSR and TD-DSR for ASIC VLSI circuits and complete detailed routing algorithms ROAD and ROAD-HOP for FPGAs and C-TD-DSR for ASIC VLSI circuits. The complete routers are obtained by innovative repeated applications of incremental routing algorithms. ROAD is a track-optimal detailed router which does not depend on the order of routing, a quality that previous (R&R-based) detailed routers lack. With various optimality-preserving speedup methods, ROAD is almost 13 times faster than the state-of-the-art flat router VPR and has the same quality of results. In order to further reduce the number of tracks, a hop-based detailed router (ROAD-HOP) is also developed. When compared with the previous best hop-based detailed router SEGA, ROAD-HOP is 7% and 33% (51%) better in terms of the number of tracks used and the average (longest) net delay, respectively. The second part of this dissertation addresses incremental and complete routing algorithms for VLSI ASIC circuits. A gridless incremental routing algorithm DSR, and its timing-driven (TD) counterpart, TD-DSR, are presented. A novel depth-first-search controlled process is used in DSR which keeps track of the nets that are perturbed (in order to make space for near-optimal routing of new nets) and does not allow their lengths and topologies to change beyond pre-set limits. To address circuit speed, a timing-driven incremental algorithm TD-DSR is developed which can quickly determine if incrementally adding a pin to a partial routing tree for a new net, or rerouting a segment of an existing net, satisfies the slacks of all connected pins of the net. Experimental results reveal that DSR and TD-DSR's failure rates, in terms of the number of unrouted nets and slack violations (zero for TD-DSR), are far smaller compared to well-known incremental routers Std and R&R, and their timing-driven versions. In the last part of this dissertation, we develop a complete TD router, C-TD-DSR, which couples a bootstrapping phase with a repetitive application of TD-DSR augmented with “balancing metrics” to facilitate shorter interconnect lengths for the remaining pins of the net. Experimental results obtained are very promising and much better than one of the best-known TD algorithms SOAR.