Design And Simulation of Binary Tree Comparators using Constant Delay Logic in 180nm Technology

A binary tree based 8 bit comparator with constant delay (CD) logic is presented in this paper. The constant delay logic used in the comparator design predischarges the output to logic 0 and makes a transition to logic 1 through a critical path clocked PMOS transistor for an NMOS transistor network. This logic is twice faster than a dynamic logic gate during its D to Q operation mode for a complex logic like a two bit binary comparator. The proposed comparator architecture has two stages, where the first stage utilizes a tree structure designed using a static logic to achieve low power consumption while the second stage utilizes a high performance CD logic without sacrificing the overall energy efficiency. Design and analysis of the Comparators has been carried out in Mentor Graphics ELDO Simulator using 180nm technology.