Providing a formal linkage between MDG and HOL
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[1] Gerard J. Holzmann,et al. Design and validation of computer protocols , 1991 .
[2] Tomás E. Uribe. Combinations of Model Checking and Theorem Proving , 2000, FroCoS.
[3] Thomas Kropf. Formal Hardware Verification: Methods and Systems in Comparison , 1997 .
[4] Jørn Lind-Nielsen,et al. BuDDy : A binary decision diagram package. , 1999 .
[5] Peter V. Homeier,et al. A Mechanically Verified Verification Condition Generator , 1995, Comput. J..
[6] William D. Young,et al. A mechanically verified code generator , 1989, Journal of Automated Reasoning.
[7] Joakim von Wright. Representing Higher-Order Logic Proofs in HOL , 1994, TPHOLs.
[8] Anna Philippou,et al. Tools and Algorithms for the Construction and Analysis of Systems , 2018, Lecture Notes in Computer Science.
[9] Hasan Amjad,et al. Programming a Symbolic Model Checker in a Fully Expansive Theorem Prover , 2003, TPHOLs.
[10] John McCarthy,et al. Correctness of a compiler for arithmetic expressions , 1966 .
[11] Michael J. C. Gordon,et al. Reachability Programming in HOL98 Using BDDs , 2000, TPHOLs.
[12] Thomas F. Melham. Higher Order Logic and Hardware Verification , 1993, Cambridge Tracts in Theoretical Computer Science.
[13] Xiaoyu Song,et al. Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs , 1998, CAV.
[14] Sofiène Tahar,et al. Three Approaches to Hardware Verification: HOL, MDG and VIS Compared , 1998, FMCAD.
[15] Wai Wong,et al. Validation of HOL Proofs by Proof Checking , 1999, Formal Methods Syst. Des..
[16] Natarajan Shankar,et al. An Integration of Model Checking with Automated Proof Checking , 1995, CAV.
[17] Randal E. Bryant,et al. Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.
[18] Randal E. Bryant,et al. Formal verification by symbolic evaluation of partially-ordered trajectories , 1995, Formal Methods Syst. Des..
[19] Richard J. Boulton,et al. Experience with Embedding Hardware Description Languages in HOL , 1992, TPCD.
[20] Natarajan Shankar,et al. Using Decision Procedures with a Higher-Order Logic , 2001, TPHOLs.
[21] Philip A. Collier. Simple Compiler correctness - A Tutorial on the Algebraic Approach , 1986, Aust. Comput. J..
[22] R. A. C. S. A. Mat.. Towards the Automated Synthesis of a Gröbner Bases Algorithm , 2004 .
[23] Tom Melham,et al. Hardware Verification using Higher−Order Logic , 1986 .
[24] Alan J. Hu. Formal hardware verification with BDDs: an introduction , 1997, 1997 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM. 10 Years Networking the Pacific Rim, 1987-1997.
[25] Xiaoyu Song,et al. Multiway Decision Graphs for Automated Hardware Verification , 1997, Formal Methods Syst. Des..
[26] Michael J. C. Gordon,et al. Edinburgh LCF: A mechanised logic of computation , 1979 .
[27] Andrew Adams,et al. Computer Algebra Meets Automated Theorem Proving: Integrating Maple and PVS , 2001, TPHOLs.
[28] Sofiène Tahar,et al. Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs , 1996, FMCAD.
[29] Sofiène Tahar,et al. Hierarchical Verification Using an MDG-HOL Hybrid Tool , 2001, CHARME.
[30] Joe Hurd. Integrating Gandalf and HOL , 1999, TPHOLs.
[31] Laurian Mircea Chirica. Contributions to compiler correctness. , 1976 .
[32] Laurent Théry,et al. A Machine-Checked Implementation of Buchberger's Algorithm , 2001, Journal of Automated Reasoning.
[33] Kees Goossens,et al. Embedding hardware description languages in proof systems , 1993, CST.
[34] Jeffrey J. Joyce,et al. Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment , 1993, HUG.
[35] Sofiène Tahar,et al. Hierarchical formal verification using a hybrid tool , 2003, International Journal on Software Tools for Technology Transfer.
[36] Carl-Johan H. Seger,et al. Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving , 1999, TPHOLs.
[37] Robert S. Boyer,et al. A computational logic handbook , 1979, Perspectives in computing.
[38] Christine Paulin-Mohring,et al. The Coq Proof Assistant : A Tutorial : Version 7.2 , 1997 .
[39] Ann Blandford,et al. Using a verification system to reason about post-completion errors , 2000 .
[40] Peter J. Landin,et al. PROGRAMS AND THEIR PROOFS: AN ALGEBRAIC APPROACH, , 1968 .
[42] Carl-Johan H. Seger,et al. A simple theorem prover based on symbolic trajectory evaluation and BDD's , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[43] Carl-Johan H. Seger,et al. Symbolic Trajectory Evaluation , 1997, Formal Hardware Verification.
[44] Thomas Kropf,et al. A Unified Approach for Combining Different Formalisms for Hardware Verification , 1996, FMCAD.
[45] Michael J. C. Gordon,et al. Mechanizing programming logics in higher order logic , 1989 .
[46] M. Gordon,et al. Introduction to HOL: a theorem proving environment for higher order logic , 1993 .
[47] Sheldon B. Akers,et al. Binary Decision Diagrams , 1978, IEEE Transactions on Computers.
[48] J. Strother Moore,et al. A mechanically verified language implementation , 1989, Journal of Automated Reasoning.
[49] Robin Milner,et al. On using Edinburgh LCF to prove the correctness of a parsing algorithm , 1982 .
[50] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[51] Sofiène Tahar,et al. Formally Linking MDG and HOL Based on a Verified MDG System , 2002, IFM.
[52] A. Blandford,et al. Embedding and Veri cation of an MDG-HDL Translator in HOL , 2022 .
[53] David F. Martin,et al. Toward compiler implementation correctness proofs , 1986, TOPL.
[54] Sofiène Tahar,et al. Importing MDG Verification Results into HOL , 1999, TPHOLs.
[55] Thomas Kropf,et al. Simplifying Deep Embedding: A Formalised Code Generator , 1994, TPHOLs.
[56] Doron A. Peled,et al. Formal Verification of a Partial-Order Reduction Technique for Model Checking , 2004, Journal of Automated Reasoning.
[57] Vijay Kumar Pisini. Integration of HOL and MDG for hardware verification , 2000 .
[58] Natarajan Shankar,et al. Combining Theorem Proving and Model Checking through Symbolic Analysis , 2000, CONCUR.
[59] Lawrence Charles Paulson,et al. ML for the working programmer , 1991 .
[60] Mandayam K. Srivas,et al. A Tutorial Introduction to PVS , 1998 .
[61] Jeffrey J. Joyce,et al. Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving , 1993, 30th ACM/IEEE Design Automation Conference.
[62] M. Gordon. HOL: A Proof Generating System for Higher-Order Logic , 1988 .
[63] Ann Blandford,et al. Demonstrating the Cognitive Plausibility of Interactive System Specifications , 2000, Formal Aspects of Computing.
[64] Sofiène Tahar,et al. Providing Automated Verification in HOL Using MDGs , 2004, ATVA.
[65] M. Byrne,et al. A Working Memory Model of a Common Procedural Error , 1997 .
[66] Carl-Johan H. Seger,et al. Formal verification of iterative algorithms in microprocessors , 2000, Proceedings 37th Design Automation Conference.
[67] Richard J. Boulton,et al. The PROSPER Toolkit , 2000, TACAS.
[68] Ann Blandford,et al. Detecting Multiple Classes of User Errors , 2001, EHCI.
[69] Sofiène Tahar,et al. Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[70] Ann Blandford,et al. Reasoning about order errors in interaction , 2000 .
[71] F. Lockwood Morris,et al. Advice on structuring compilers and proving them correct , 1973, POPL.
[72] César Muñoz,et al. An Overview of SAL , 2000 .
[73] John Harrison,et al. A Skeptic's Approach to Combining HOL and Maple , 1998, Journal of Automated Reasoning.
[74] André Heck,et al. Introduction to Maple , 1993 .
[75] Mark Aagaard,et al. Divider Circuit Verification with Model Checking and Theorem Proving , 2000, TPHOLs.
[76] David A. Basin,et al. Verified Bytecode Model Checkers , 2002, TPHOLs.
[77] Thomas F. Melham. Integrating Model Checking and Theorem Proving in a Reflective Functional Language , 2004, IFM.
[78] Sofiène Tahar,et al. Verification of the MDG Components Library in HOL , 1998 .