Barrel shifter design, optimization, and analysis

Barrel shifters are arithmetic and logic circuits that may be utilized to shift or rotate data in a general-purpose microprocessor or digital signal processor. This thesis proposes and analyzes various methods of implementing barrel shifters. The purpose of this thesis is to understand the tradeoffs of various barrel shifter design approaches in order to recognize where each may be most useful. Each design is a compromise between gate count and critical path latency. In an attempt to reduce both, the proposed designs utilize a number of innovative design techniques. The techniques can be divided into two categories: those addressing uni-directional result computation and those providing the logic necessary to implement all operations with' uni-directional hardware support. Four design schemes were employed to test each of the techniques; Mux-based Data Reversal, Mask-based Data Reversal, Mask-based Two's Complement, and Mask-based One's Complement. The mux-based and mask-based descriptor indicates the uni-directional result computation method, while the rest specify the mechanism used to emulate bi-directional operations with uni-directional hardware support. Analysis of each design reveals some unique fmdings. First of all, the designs using the two's complement and one's complement mechanisms were found to have a critical path latency much higher than expected, thus they are of very limited use unless the shift/rotate amount arrives earlier than the data to be shifted or rotated. Second, the optimal designs were found to be the Mux-based Data Reversal and Mask-based Data Reversal approaches. Each had comparable area-delay products. If gate count minimization is the primary concern, then the mux-based approach is preferred. Likewise, critical path latency minimization is achieved with the maskbased approach. Thus, no single design is preferred for all circumstances. Instead, use is highly dependent on the particular demands placed on the circuit.