14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.