Investigation on the Suitability of Vertical MOSFET's for High Speed (RF) CMOS Applications

Despite higher intrinsic capacitances, than in planar MOS transistor, vertical MOSFET can be very attractive for high speed CMOS IC due to enhanced current drivability. It is shown that in real <;ircuits (especially in those heavy loaded by interconnect capacitances) the improved current drivability prevails over the intrinsic capacitances, thus allOWing higher circuit frequency. The paper also reports on our first experiments aimed at optimized vertical MOS architecture. In particular, we have managed to reduce overlap capacitances, which are crucial for vertical transistor dynamic performance, by a modification of the oxide growth process prior to polysilicon gate deposition. The capacitance reduction factor of as many as 2 is obtained on our samples. We demonstrate that with this and other improvements vertical MOSFET is capable of pushing forward the point, at which interconnects dominate the circuit speed, by as many as two generations (from O.12Jlln to O.OBJlln).