Implementing Intrusion Detection System for Multicore Processor

Multi-core processors represent a major evolution in computing hardware technology. Multi-core provides a network security application with more processing power from the hardware perspective. However, there are still significant software design challenges that must be overcome. In this paper, we present new architecture for multi-core supported Intrusion Detection System, which aims at providing network security processing without causing performance penalty to normal network operations. While hardware-based parallelisms have shown their advantage on throughput performance, parallelisms based multi-core provides more flexible, high performance, comprehensive, intelligent, and scalable solutions to network security applications. The Intrusion Detection System that we presented in this paper also protect the multi core systems from Real Time attacks and Packet Filtrations with high performance without any penalty.

[1]  B. Achiriloaie,et al.  VI REFERENCES , 1961 .

[2]  James R. Larus,et al.  Software and the Concurrency Revolution , 2005, ACM Queue.

[3]  Fabrizio Petrini,et al.  Accelerating Real-Time String Searching with Multicore Processors , 2008, Computer.

[4]  Dean M. Tullsen,et al.  Simultaneous multithreading: a platform for next-generation processors , 1997, IEEE Micro.

[5]  John W. Lockwood,et al.  Rethinking Hardware Support for Network Analysis and Intrusion Prevention , 2006, HotSec.

[6]  John W. Lockwood,et al.  Deep packet inspection using parallel bloom filters , 2004, IEEE Micro.

[7]  Yan Luo,et al.  Efficient memory utilization on network processors for deep packet inspection , 2006, 2006 Symposium on Architecture For Networking And Communications Systems.

[8]  Charlie Johnson,et al.  Future processors: flexible and modular , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[9]  Yan Luo,et al.  DPICO: a high speed deep packet inspection engine using compact finite automata , 2007, ANCS '07.

[10]  Bin Liu,et al.  A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection , 2006, IEEE Journal on Selected Areas in Communications.