Test Scheduling for Memory Cores with Built-In Self-Repair

This paper presents a stage-based test scheduling for memory cores with BISR scheme under power constraint. We introduce a model to compute the expected test time for a given test schedule for memory cores with BISR scheme based on pass probabilities, and propose a test scheduling algorithm to minimize the expected test time. Experimental results show a significant expected test time reduction compared to the core-based test scheduling method which minimizes the test time.

[1]  Nilanjan Mukherjee,et al.  Resource allocation and test scheduling for concurrent test of core-based SOC design , 2001, Proceedings 10th Asian Test Symposium.

[2]  Steffen Paul,et al.  Memory built-in self-repair using redundant words , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[3]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[4]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[5]  Erik Jan Marinissen,et al.  On using rectangle packing for SOC wrapper/TAM co-optimization , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[6]  Nilanjan Mukherjee,et al.  Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm , 2002, Proceedings. International Test Conference.

[7]  Robert C. Aitken.  A modular wrapper enabling high speed BIST and repair for small wide memories , 2004, 2004 International Conferce on Test.

[8]  Wei-Lun Wang.  March based memory core test scheduling for SOC , 2004, 13th Asian Test Symposium.

[9]  Hideo Fujiwara,et al.  A memory grouping method for sharing memory BIST logic , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[10]  Yervant Zorian,et al.  Testing Embedded-Core-Based System Chips , 1999, Computer.

[11]  Robert Aitken.  A modular wrapper enabling high speed BIST and repair for small wide memories , 2004 .

[12]  Krishnendu Chakrabarty,et al.  Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs , 2006, 2006 IEEE International Test Conference.

[13]  Erik Jan Marinissen,et al.  Effective and efficient test architecture design for SOCs , 2002, Proceedings. International Test Conference.

[14]  Erik Jan Marinissen,et al.  Test scheduling for modular SOCs in an abort-on-fail environment , 2005, European Test Symposium (ETS'05).

[15]  Julien Pouget,et al.  Abort-on-Fail Based Test Scheduling , 2005, J. Electron. Test..

[16]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2002, J. Electron. Test..

[17]  Youn-Long Lin,et al.  Test scheduling of BISTed memory cores for SoC , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[18]  Jin-Fu Li,et al.  A built-in self-repair design for RAMs with 2-D redundancy , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Yervant Zorian,et al.  Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.

[20]  Hideo Fujiwara,et al.  Efficient test solutions for core-based designs , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.