A Research Methodology for Neural Network Based on VHDL

This paper presents a new research methodology for Artificial Neural Network(ANN) VHDL simulation. In the current ANN, algorithms have been proposed to solve specific information processing problems through manipulation of ANNs connection weights. They are not capable of solving effectively problems in ANN as a whole.At the same time,VHDL language is only used to put an ANN into hardware.This paper analyzes the VHDL languages advantages in ANN simulation and presents a new parellel dynamic stimulate delay ANN model using VHDL simulation.In this model, algorithms and structures are merged in the sense as the activity of each neuron relies soly on its inputs, while the function of ANN is determined by the connections between those neurons.This method considers the ANN as a whole and can simulate the biology NN and can widen the ANN research range.