Post-synthesis back-annotation of timing information in behavioral VHDL

Abstract This paper presents an approach to back-annotation of timing information in behavioral VHDL descriptions. In our approach, a behavioral VHDL description specifies the functionality and timing constraints of a design which is synthesized by a high-level synthesis tool. After synthesis the timing information of the design is back-annotated to the original VHDL description which is then used for simulation. A distinct feature of our approach is that it does not rely on the so called well-timed assumption which requires that the execution of every alternative path should take exactly the same time. This reflects the synthesis strategy adopted by our system, namely different execution times can be synthesized for the alternative paths in a constrained statement sequence, as long as all these times satisfy the user-specified timing requirements. Thus, our back-annotation strategy solves the tracing of the actually executed path through a time-constrained sequence and the dynamic selection of the respective synthesized time for simulation. The elaborated algorithms are illustrated by examples.