Analysis and Design of Charge Pumps for Telecommunication Applications

This chapter addresses modern telecommunication integrated circuits from the synthesizer focal point; in particular it concentrates at the analysis and the design of integrated charge pump circuit blocks. It presents an overview of charge pump topologies in addition to a coherent analysis of the associated benefits and shortcomings of all circuit alternatives. Moreover a novel favorable charge pump combining current steering techniques with well utilized unity gain buffers in a novel, noiseless feedback scheme, is introduced to improve on switching speed, inherent charge pump ac noise, dead-zone interval, therefore overall steady state aliased loop noise; while on the other hand this charge pump exhibits superb DC matching characteristics in a wide output voltage range. Furthermore a well documented estimation of the active devices that contributes mostly to the overall charge pump noise performance is presented. Also an associated mathematical analysis concerning the frequency content of the charge pump noise current is given. This proposed topology manifests its applicability to charge pump alternatives, as it is demonstrated by the associated simulation results from a 0.18μm design. Because of the low-noise and accurate properties of this improved charge pump, it is ideally suited to modern telecommunication standards synthesizer realizations.

[1]  Herbert Taub,et al.  Principles of communication systems , 1970 .

[2]  Bang-Sup Song,et al.  A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3b 3rd-order ΔΣ modulator , 2000 .

[3]  Pavan Kumar Hanumolu,et al.  Analysis of charge-pump phase-locked loops , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[5]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz of lock range for microprocessors , 1992 .

[6]  M. Steyaert,et al.  A fully integrated CMOS DCS-1800 frequency synthesizer , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[7]  J. F. Parker,et al.  A 1.6-GHz CMOS PLL with on-chip loop filter , 1998, IEEE J. Solid State Circuits.

[8]  Wonchan Kim,et al.  Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer , 2005 .

[9]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[10]  B.-S. Song,et al.  A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator , 2000, IEEE Journal of Solid-State Circuits.

[11]  Mohamed I. Elmasry,et al.  A low-power CMOS frequency synthesizer design methodology for wireless applications , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[12]  Edgar Sanchez-Sinencio,et al.  A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier , 2003, IEEE J. Solid State Circuits.

[13]  Joonbae Park,et al.  Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer , 2005, IEEE Journal of Solid-State Circuits.

[14]  W. Rhee,et al.  Design of high-performance CMOS charge pumps in phase-locked loops , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[15]  Behzad Razavi.  A Modeling Approach for ¿¿ FractionalN Frequency Synthesizers Allowing Straightforward Noise Analysis , 2003 .

[16]  Nikolaus Klemmer,et al.  Enhanced phase noise modeling of fractional-N frequency synthesizers , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  M. Steyaert,et al.  A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800 , 2002, IEEE J. Solid State Circuits.

[18]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[19]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[20]  H.R. Rategh,et al.  A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver , 2000, IEEE Journal of Solid-State Circuits.

[21]  A.L.S. Loke,et al.  A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking , 2006, IEEE Journal of Solid-State Circuits.

[22]  R.C. Chang,et al.  A new low-voltage charge pump circuit for PLL , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[23]  B. Razavi.  Monolithic phase-locked loops and clock recovery circuits : theory and design , 1996 .

[24]  José Silva-Martínez,et al.  Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[25]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[26]  I. Seto,et al.  A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer , 2008, IEEE Journal of Solid-State Circuits.

[27]  Kyoungho Woo,et al.  Fast-Lock Hybrid PLL Combining Fractional- $N$ and Integer-$N$ Modes of Differing Bandwidths , 2008, IEEE Journal of Solid-State Circuits.

[28]  K. Halonen,et al.  A Low-Power Phase-Locked Loop for UWB Applications , 2006, 2006 NORCHIP.

[29]  Chih-Ming Hung,et al.  A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop , 2002, IEEE J. Solid State Circuits.

[30]  Mehmet Soyuer,et al.  A Fully Monolithic 1.25ghz cmos Frequency Synthesizer , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[31]  Mitchell D. Trott,et al.  A Modeling Approach for – Fractional- N Frequency Synthesizers Allowing Straightforward Noise Analysis , 2001 .

[32]  E. L. Hudson,et al.  A variable delay line PLL for CPU-coprocessor synchronization , 1988 .