The defect-sensitivity effect of memory chips

Three effects appear to influence the yield of digital memory chips. In the first effect, yields appear to decrease faster with chip area than is predicted with simple yield models. Although this effect has been described briefly before, more supporting data are given and the applicable yield models are derived from these data. The second effect suggests that the random-defect yield for a chip does not change when its area is shrunk by decreasing the minimum design rules. Although experimental verification for this is limited, it leads to a third effect, namely, that yield can be modeled by the number of circuits. This effect is amply verified with data.