Image processing applications are common in every field of our daily life. However, most of them are very complex and contain several tasks with different complexities which result in varying requirements for computing architectures. Nevertheless, a general processing scheme in every image processing application has a similar structure, called image processing pipeline: (1) capturing an image, (2) pre-processing using local operators, (3) processing with global operators and (4) post-processing using complex operations. Therefore, application-specialized hardware solutions based on heterogeneous architectures are used for image processing. Unfortunately the development of applications for heterogeneous hardware architectures is challenging due to the distribution of computational tasks among processors and programmable logic units. Nowadays, image processing systems are started from scratch which is time-consuming, error-prone and inflexible. A new methodology for modeling and implementing is needed in order to reduce the development time of heterogenous image processing systems. This paper introduces a new holistic top down approach for image processing systems. Two challenges have to be investigated. First, designers ought to be able to model their complete image processing pipeline on an abstract layer using UML. Second, we want to close the gap between the abstract system and the system architecture.
[1]
S. Pizer,et al.
The Image Processing Handbook
,
1994
.
[2]
Wayne Luk,et al.
Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming
,
2006,
2006 International Conference on Field Programmable Logic and Applications.
[3]
Donald G. Bailey,et al.
Design for Embedded Image Processing on FPGAs: Bailey/Design for Embedded Image Processing on FPGAs
,
2011
.
[4]
Da He,et al.
Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems
,
2010,
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[5]
Donald G. Bailey,et al.
Design for Embedded Image Processing on FPGAs
,
2011
.