A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031 mm2. Average execution time is reduced to 31% compared to that using one chip.

[1]  Tadahiro Kuroda,et al.  An 11Gb/s Inductive-Coupling Link with Burst Transmission , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Tadahiro Kuroda,et al.  A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  A. Parimala,et al.  MuCCRA chips: Configurable dynamically-reconfigurable processors , 2007, 2007 IEEE Asian Solid-State Circuits Conference.