Analyzing and increasing soft error resilience of Deep Neural Networks on ARM processors

Abstract Deep Neural Networks (DNNs) have been successfully deployed in safety-critical applications due to the capability of computing in complex tasks. Because of low energy, ARM (Advanced RISC Machine) processors are used for DNNs in embedded applications. However, in harsh environments, soft errors induced by radiation strikes may cause Silent Data Corruptions (SDCs) and Detected Unrecoverable Errors (DUEs). In this work, for DNNs, we evaluate the soft error resilience of the register file and analyze the impact of compiler optimizations. The results show that compiler optimization significantly degrades the reliability of DNNs. Furthermore, we track SDC propagation and record execution time for each layer. The results indicate that for most DNNs, convolutional layers are the most vulnerable because they are the most time-consuming parts. For instructions, we evaluate Program Vulnerability Factor (PVF) contributions of instructions and identify the vulnerable instructions that may cause critical SDCs. To mitigate critical SDCs, we propose two efficient approaches: 1) selective kernel hardening and 2) Symptom-based Duplication with Comparison (SDWC). The former reduces SDCs by an order of magnitude and incurs 33.56% time overhead. The second approach reduces critical SDCs to 0 and incurs less than 10% time overhead. For DUEs, we propose an idempotency-based recovery. Our approach mitigates more than 92.2% DUEs and incurs 3.43% latency overhead on average.

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