Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor

This paper describes the design and implementation of the vector scalar unit (VSU) in the first-generation CELL processor. VSU executes floating-point and vector media extension instructions. VSU contains 1.7 million transistors and occupies an area of 3.1 mm/sup 2/ in a 90nm PD-SOI technology. Extensive static and dynamic circuit techniques are used to optimize performance while minimizing area and power simultaneously. Full functionality is observed at 4.76 GHz, 1.3V supply and a chip temperature of 68/spl deg/C.

[1]  S. Asano,et al.  The design and implementation of a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2]  H. H. Chen,et al.  CPAM: a common power analysis methodology for high-performance VLSI design , 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).

[3]  Peter A. Sandon,et al.  PowerPC 970 in 130nm and 90nm technologies , 2004 .

[4]  J.B. Kuang,et al.  A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..