An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast Fourier Transform (FFT) is a critical block as it occupies large area and consumes more power. In this paper, we present an area-efficient and low power 16-bit word-width 64-point radix-22 and radix-23 pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband. The designs are derived from radix-2k algorithm and adopt a Single-Path Delay Feedback (SDF) architecture for hardware implementation. To eliminate the complex multipliers and read-only memory (ROM) which is used for internal storage of twiddle factor coefficients, the proposed 64-point FFT employs a Canonical Signed Digit (CSD) complex constant multiplier using adders, multiplexers and shifters. The complex constant multiplier (CCM) is modified using common sub-expression sharing block that reduces the area of the design. The proposed radix-22 and radix-23 pipelined FFT architectures are modeled and implemented using TSMC 180nm CMOS technology with a supply voltage of 1.8V. The implementation results show that the proposed architectures significantly reduces the hardware cost and power consumption in comparison to existing 64-point FFT architectures. HighlightsWe present R22SDF and R23SDF pipelined 64-point FFT architectures that are suitable for OFDM based wireless systems.Proposed architecture employs radix-2k algorithm and pipeline single-path delay feedback architecture.The complex multipliers are realized using modified CSD complex constant multipliers (CCM1, CCM2 and CCM3).Implementation results show reduction in hardware cost and power consumption of the proposed architectures .

[1]  Chin-Teng Lin,et al.  A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[2]  Chao-Ming Chen,et al.  Energy-efficient 128∼2048/1536-point FFT processor with resource block mapping for 3GPP-LTE system , 2010, The 2010 International Conference on Green Circuits and Systems.

[3]  Yunho Jung,et al.  New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications , 2003, IEEE Trans. Consumer Electron..

[4]  Yasuhiko Nakashima,et al.  ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system , 2016, 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX).

[5]  Pao-Ann Hsiung,et al.  A low-power 64-point pipeline FFT/IFFT processor for OFDM applications , 2011, IEEE Transactions on Consumer Electronics.

[6]  Sang-In Cho,et al.  A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems , 2010 .

[7]  S. K. Nandy,et al.  Design of a low power 64 point FFT architecture for WLAN applications , 2013, 2013 25th International Conference on Microelectronics (ICM).

[8]  U. Jagdhold,et al.  A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM , 2004, IEEE Journal of Solid-State Circuits.

[9]  Bingsheng He,et al.  A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Chein-Wei Jen,et al.  High-speed and low-power split-radix FFT , 2003, IEEE Trans. Signal Process..

[11]  Hanho Lee,et al.  A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[12]  Myoung Seob Lim,et al.  New Radix-2 to the 4th Power Pipeline FFT Processor , 2005, IEICE Trans. Electron..

[13]  Shousheng He,et al.  Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[14]  Chin-Long Wey,et al.  Efficient memory-based FFT processors for OFDM applications , 2007, 2007 IEEE International Conference on Electro/Information Technology.

[15]  J. Tukey,et al.  An algorithm for the machine calculation of complex Fourier series , 1965 .

[16]  T. Arslan,et al.  Novel low power pipelined FFT based on subexpression sharing for wireless LAN applications , 2004, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004..

[17]  J. F. Sevillano,et al.  Radix $r^{k} $ FFTs: Matricial Representation and SDC/SDF Pipeline Implementation , 2009, IEEE Transactions on Signal Processing.

[18]  Richard M. Jiang,et al.  An Area-Efficient FFT Architecture for OFDM Digital Video Broadcasting , 2007, IEEE Transactions on Consumer Electronics.

[19]  Shang-Ho Tsai,et al.  MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Shousheng He,et al.  Designing pipeline FFT processor for OFDM (de)modulation , 1998, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167).

[21]  Mats Torkelson,et al.  A new approach to pipeline FFT processor , 1996, Proceedings of International Conference on Parallel Processing.

[22]  Ade Irawan,et al.  64-point fast efficient FFT architecture using Radix-23 single path delay feedback , 2009, 2009 International Conference on Electrical Engineering and Informatics.