A VHDL-based approach for power estimation of embedded systems

Abstract Power dissipation has become one of the main constraints during the design of embedded systems and VLSI circuits in the recent years, due to continuous increase of the integration level and the operating frequency. The aim of this paper is to present an innovative conceptual framework suitable for achieving accurate and efficient estimation of power dissipation for embedded systems described in VHDL at the behavioral and Register-Transfer levels. The goal is to provide the designer with the capability of analyzing and comparing different solutions in the architectural design space before the synthesis. The analytical power model is hierarchical, considering the different parts of the target system architecture, mainly the data-path, the memory, the control logic and the embedded core processor. Experimental results are obtained by applying the proposed power model to benchmark circuits.

[1]  Massoud Pedram,et al.  Power conscious CAD tools and methodologies: a perspective , 1995, Proc. IEEE.

[2]  Paul E. Landman.  High-level power estimation , 1996, ISLPED.

[3]  Donatella Sciuto,et al.  Tosca: A Pragmatic Approach To Co-Design Automation Of Control-Dominated Systems , 1996 .

[4]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[5]  Thomas D. Burd,et al.  Energy efficient CMOS microprocessor design , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[6]  Cristina Silvano,et al.  A conceptual analysis framework for low power design of embedded systems , 1996, 1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon.

[7]  Kaushik Roy,et al.  SYCLOP: synthesis of CMOS logic for low power applications , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[8]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Daniel D. Gajski,et al.  Area and performance estimation from system-level specifications , 1992 .

[10]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Ibrahim N. Hajj,et al.  Probabilistic simulation for reliability analysis of CMOS VLSI circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Luca Benini,et al.  State assignment for low power dissipation , 1995 .

[13]  Bruno O. Shubert,et al.  Random variables and stochastic processes , 1979 .

[14]  J. Rabaey,et al.  Behavioral Level Power Estimation and Exploration , 1997 .

[15]  Sharad Malik,et al.  A Survey of Optimization Techniques Targeting Low Power VLSI Circuits , 1995, 32nd Design Automation Conference.

[16]  Enrico Macii.  Sequential synthesis and optimization for low power , 1997 .

[17]  Wayne Wolf,et al.  Hardware-software co-design of embedded systems , 1994, Proc. IEEE.

[18]  Giovanni De Micheli,et al.  Hardware/Software Co-Design: Application Domains and Design Technologies , 1996 .

[19]  Shin Min Kang,et al.  Low-power state assignment for finite state machines , 1994 .

[20]  Chi-Ying Tsui,et al.  Low power state assignment targeting two-and multi-level logic implementations , 1994, ICCAD.

[21]  VlJAY NAGASAMY,et al.  Specification, planning, and synthesis in a VHDL design environment , 1992, IEEE Design & Test of Computers.

[22]  John G. Proakis,et al.  Probability, random variables and stochastic processes , 1985, IEEE Trans. Acoust. Speech Signal Process..

[23]  Jan M. Rabaey,et al.  Power estimation for high level synthesis , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[24]  M. Lynn.  Hawaii International Conference on System Sciences , 1996 .

[25]  Jan M. Rabaey,et al.  Activity-sensitive architectural power analysis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[28]  Amnon Naamad,et al.  Statemate: a working environment for the development of complex reactive systems , 1988, ICSE '88.