Electron beam lithography for 0.13 μm manufacturing

General requirements for the use of electron beam lithography in direct write manufacturing of silicon integrated circuits are discussed. 50 keV is suggested as an optimum beam energy, since this is the minimum beam energy that can achieve high aspect ratio structures (4:1) in single layer resists in a manufacturing environment. Higher beam energies result in an inefficient exposure process requiring larger currents; this combination will lead to excessive resist and wafer heating. Lower voltages will require the use of top surface imaging or multilayer resists, which have concerns of processing complexity, resist charging, and defects. At 50 keV, some form of proximity correction is required to achieve reasonable control of critical dimensions. While one of the principle arguments for low voltage lithography is that it avoids the need for proximity correction, proximity correction is a solvable problem for large chips and is therefore a less risky approach than developing a reliable surface imaging resis...