2009 EDAA PhD Forum at DATE

[1]  Luca Benini,et al.  Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints , 2009, 2009 International Conference on Complex, Intelligent and Software Intensive Systems.

[2]  Chien-Nan Jimmy Liu,et al.  Accurate behavioral modeling approach for PLL designs with supply noise effects , 2005, BMAS 2005. Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005..

[3]  Harald Devos,et al.  Loop Transformations for the Optimized Generation of Reconfigurable Hardware , 2008 .