Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications

This paper provides a comprehensive review of Three-Independent-Gate Field-Effect Transistors (TIGFETs). In parallel to the focus on transistor scaling, an alternative approach to push further the performance of computing systems consists in increasing the functionalities of the basic transistors by means of additional gate controls. TIGFETs belong to this category of devices and can achieve different modes of operation according to the bias of the gate terminals. In particular, these devices are capable of (i) device-level polarity control, (ii) dynamic threshold modulation and (iii) subthreshold slope tuning down to ultra-steep-slope operation. The functionality increase at the device level leads to several design opportunities for digital, analog and RF applications.

[1]  Giovanni De Micheli,et al.  Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Luca Gaetano Amarù,et al.  Digital, analog and RF design opportunities of three-independent-gate transistors , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[3]  Giovanni De Micheli,et al.  Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Takayuki Konishi,et al.  Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology , 2011, IEICE Trans. Electron..

[5]  G. De Micheli,et al.  Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.

[6]  Mohamed I. Elmasry,et al.  A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[7]  Hao Lu,et al.  Universal analytic model for tunnel FET circuit simulation , 2015 .

[8]  A. Burg,et al.  A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS , 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

[9]  Stefan Slesazeck,et al.  Reconfigurable silicon nanowire transistors. , 2012, Nano letters.

[10]  Mikael Östling,et al.  Low-Frequency Noise in Advanced MOS Devices , 2007 .

[11]  Giovanni De Micheli,et al.  Multiple Independent Gate FETs: How many gates do we need? , 2015, The 20th Asia and South Pacific Design Automation Conference.

[12]  Paul Jespers.  The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches , 2009 .

[13]  G. De Micheli,et al.  Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages , 2014, IEEE Transactions on Electron Devices.

[14]  A. Rogalski,et al.  Terahertz detectors and focal plane arrays , 2011 .

[15]  P. Földesy.  Terahertz responsivity of field-effect transistors under arbitrary biasing conditions , 2013 .

[16]  Mohamed I. Elmasry,et al.  A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element , 1996, ISLPED.

[17]  W. Knap,et al.  Terahertz responsivity of field effect transistors versus their static channel conductivity and loading effects , 2011 .

[18]  Denis Flandre,et al.  A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA , 1996, IEEE J. Solid State Circuits.

[19]  Giovanni De Micheli,et al.  Advanced system on a chip design based on controllable-polarity FETs , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  G. De Micheli,et al.  On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET , 2015, IEEE Journal of the Electron Devices Society.

[21]  O. Rozeau,et al.  28nm FDSOI technology platform for high-speed low-voltage digital applications , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[22]  G. De Micheli,et al.  A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current , 2014, 2014 IEEE International Electron Devices Meeting.

[23]  Ogun Turkyilmaz,et al.  Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[24]  Giovanni De Micheli,et al.  Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[25]  Guowu Yang,et al.  Majority-based reversible logic gates , 2005, Theor. Comput. Sci..

[26]  Giovanni De Micheli,et al.  TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[27]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[28]  H. Roskos,et al.  Terahertz responsivity and low-frequency noise in biased silicon field-effect transistors , 2013 .

[29]  J. Jomaah,et al.  Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs , 2012 .

[30]  Cor Claeys,et al.  Low frequency noise characterization in n-channel FinFETs , 2012 .