A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula>) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> variation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce required <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> margin reduction, and continuous <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> reduction corresponding to a 94% <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> margin recovery or an equivalent <inline-formula> <tex-math notation="LaTeX">$3.2\times $ </tex-math></inline-formula> increase in the operating clock frequency (<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm{ clk}}$ </tex-math></inline-formula>).