Fault Location in FPGA-Based Reconfigurable Systems

In this paper, we describe a new technique for locating faulty Lookup Tables (LUTs) in FPGA-based reconfigurable systems. The technique is in-place (does not alter the routing structure of the LUT network) and is based on pseudo-exhaustive Built-In Self-Test where each configured LUT is tested exhaustively. Our technique involves selective reprogramming of the LUTs and takes advantage of partial reconfiguration when it is available.

[1]  William P. Marnane,et al.  Incoming inspection of FPGA's , 1993, Proceedings ETC 93 Third European Test Conference.

[2]  Charles E. Stroud,et al.  BIST-based diagnostics of FPGA logic blocks , 1997, Proceedings International Test Conference 1997.

[3]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[4]  Fabrizio Lombardi,et al.  On the diagnosis of programmable interconnect systems: Theory and application , 1996, Proceedings of 14th VLSI Test Symposium.

[5]  Fabrizio Lombardi,et al.  Diagnosing Programmable Interconnect Systems for FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[6]  Yervant Zorian,et al.  Testing the Interconnect of RAM-Based FPGAs , 1998, IEEE Des. Test Comput..

[7]  Arthur D. Friedman,et al.  Easily Testable Iterative Systems , 1973, IEEE Transactions on Computers.

[8]  Tong Liu,et al.  Diagnosis of interconnects and FPICs using a structured walking-1 approach , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[9]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[10]  Edward J. McCluskey,et al.  Logic design principles - with emphasis on testable semicustom circuits , 1986, Prentice Hall series in computer engineering.

[11]  Edward J. McCluskey.  Verification Testing , 1982, 19th Design Automation Conference.

[12]  Hideo Fujiwara,et al.  Universal Fault Diagnosis for Lookup Table FPGAs , 1998, IEEE Des. Test Comput..

[13]  Ping Chen,et al.  Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) , 1996, Proceedings of 14th VLSI Test Symposium.

[14]  Miodrag Potkonjak,et al.  Efficiently supporting fault-tolerance in FPGAs , 1998, FPGA '98.

[15]  Edward J. McCluskey,et al.  Dependable adaptive computing systems-the ROAR project , 1998, SMC'98 Conference Proceedings. 1998 IEEE International Conference on Systems, Man, and Cybernetics (Cat. No.98CH36218).

[16]  Maya Gokhale,et al.  The NAPA adaptive processing architecture , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[17]  Sying-Jyan Wang,et al.  Test and diagnosis of faulty logic blocks in FPGAs , 1997, ICCAD 1997.

[18]  Edward J. McCluskey,et al.  Design for Autonomous Test , 1981, IEEE Transactions on Computers.

[19]  Yervant Zorian,et al.  Test of RAM-based FPGA: methodology and application to the interconnect , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).