论文信息 - Single-event effects in 0.18 /spl mu/m CMOS commercial processes

Single-event effects in 0.18 /spl mu/m CMOS commercial processes

We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 /spl mu/m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.

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