Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout

A new methodology for hierarchical floor planning and global routing for building block layout is presented. Unlike the traditional approach, which separates placement and global routing into two consecutive stages, our approach accomplishes both jobs simultaneously in a hierarchical fashion. The global routing problem is formulated at each level as a series of the minimum Steiner tree problem in a special class of partial 3-trees, which can be solved optimally in linear time. The floor planner with a maximum of five rooms per level has been implemented in the C language, running on a VAX 8650 under 4.3 BSD UNIX. The experimental results on examples with a large number of irregular blocks show that our approach out-performs other well-known deterministic algorithms, and gives results that are comparable to random-based algorithms but with a computing time an order of magnitude less. Due to the unique goal-oriented and pattern-directed features of our floor planner, it accepts specifications for overall aspect ratio and I/O pad positions, thus making our approach suitable for hierarchical design.

[1]  Michael Burstein,et al.  Hierarchical Wire Routing , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  S. Arnborg,et al.  Characterization and recognition of partial 3-trees , 1986 .

[3]  Alfred V. Aho,et al.  Rectilinear steiner trees: Efficient special-case algorithms , 1977, Networks.

[4]  Ulrich Lauther,et al.  A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation , 1979, 16th Design Automation Conference.

[5]  John Grason.  An approach to computerized space planning using graph theory , 1971, DAC '71.

[6]  David S. Johnson,et al.  The Rectilinear Steiner Tree Problem is NP Complete , 1977, SIAM Journal of Applied Mathematics.

[7]  R. Otten.  Automatic Floorplan Design , 1982, DAC 1982.

[8]  Charles J. Colbourn,et al.  Steiner trees, partial 2-trees, and minimum IFI networks , 1983, Networks.

[9]  Donald J. ROSE,et al.  On simple characterizations of k-trees , 1974, Discret. Math..

[10]  J. Soukup.  Circuit layout , 1981, Proceedings of the IEEE.

[11]  Donald T. Tang,et al.  Hierarchical Global Wiring for Custom Chip Design , 1986, DAC 1986.

[12]  Daniel G. Schweikert.  A 2-dimensional placement algorithm for the layout of electrical circuits. , 1976, DAC '76.

[13]  Yen-Tai Lai,et al.  An Algorithm for Building Rectangular Floor-Plans , 1984, 21st Design Automation Conference Proceedings.

[14]  Bryan T. Preas,et al.  Automatic Placement A Review of Current Techniques , 1986, DAC 1986.

[15]  Tetsuo Asano,et al.  Routing Region Definition and Ordering Scheme for Building-Block Layout , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  William R. Heller,et al.  The Planar Package Planner for System Designers , 1982, DAC 1982.

[17]  Krzysztof Kozminski,et al.  An Algorithm for Finding a Rectangular Dual of a Planar Graph for Use in Area Planning for VLSI Integrated Circuits , 1984, 21st Design Automation Conference Proceedings.

[18]  Ernest S. Kuh,et al.  A Dynamic and Efficient Representation of Building-Block Layout , 1987, 24th ACM/IEEE Design Automation Conference.