Estimation of BIST Resources During High-Level Synthesis

Lower bound estimations of functional resources at various stages of high-level synthesis have been developed to guide synthesis algorithms toward optimal solutions. In this paper we present lower bounds on the number of test resources (i.e., registers that generate pseudo-random test patterns and/or compress test responses) required to test a synthesized data path using built-in self-test (BIST). The bounds on different types of test resources are proved to be individually achievable and experiments show that in most cases the bounds can be achieved simultaneously and with minimum number of functional registers. Efficient ways of computing the lower bounds are developed. The estimations are performed on scheduled data flow graphs with a given module assignment and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of BIST resources to test itself.

[1]  Alok Sharma,et al.  Estimating architectural resources and performance for high-level synthesis applications , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Alex Orailoglu,et al.  SYNCBIST: SYNthesis for concurrent built-in self-testability , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[3]  Melvin A. Breuer,et al.  Scheduling and module assignment for reducing BIST resources , 1998, Proceedings Design, Automation and Test in Europe.

[4]  Alice C. Parker,et al.  Predicting system-level area and delay for pipelined and nonpipelined designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Alice C. Parker,et al.  Data path tradeoffs using MABAL , 1991, DAC '90.

[6]  T. Kailath,et al.  VLSI and Modern Signal Processing , 1984 .

[7]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[8]  Haidar Harmanani,et al.  A data path synthesis method for self-testable designs , 1991, 28th ACM/IEEE Design Automation Conference.

[9]  Nikil D. Dutt,et al.  Comprehensive Lower Bound Estimation From Behavioral Descriptions , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[10]  Melvin A. Breuer,et al.  Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead , 1995, 32nd Design Automation Conference.

[11]  Daniel P. Siewiorek,et al.  Automated Synthesis of Data Paths in Digital Systems , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Andrzej Krasniewski,et al.  Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules , 1985, ITC.

[14]  Nilanjan Mukherjee,et al.  Arithmetic built-in self test for high-level synthesis , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[15]  Rajiv Jain,et al.  Area-time model for synthesis of non-pipelined designs , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[16]  Minjoong Rim,et al.  Estimating lower-bound performance of schedules using a relaxation technique , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[17]  B. Koenemann,et al.  Built-in logic block observation techniques , 1979 .

[18]  Christos A. Papachristou,et al.  An improved method for RTL synthesis with testability tradeoffs , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[19]  Yuan Hu,et al.  Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[20]  LaNae J. Avra,et al.  ALLOCATION AND ASSIGNMENT IN HIGH-LEVEL SYNTHESIS FOR SELF-TESTABLE DATA PATHS , 1991, 1991, Proceedings. International Test Conference.

[21]  Robert A. Walker,et al.  Computing lower bounds on functional units before scheduling , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.