Design and implementation of cost-effective IIR filter for EEG signal on FPGA

ABSTRACT Filter is unfathomably used to identify diverse human flag in genuine time. In this paper, a digital IIR filter is proposed for the fast detection of EEG signal to smooth and compress the signal. This paper intends to design a digital IIR filter based on Field Programmable Gate Array (FPGA) to get faster biomedical signals specially EEG signals. For this purpose, a high order IIR filter is introduced to make EEG signal noise free, less costly and simple. For hardware usage, FPGA load up is utilised which is a mix of various logic gates which offers economical and enduring administrations.

[1]  Anantha Chandrakasan,et al.  An energy-efficient biomedical signal processing platform , 2010, 2010 Proceedings of ESSCIRC.

[2]  Atik Mahabub Design and Implementation of a Novel Complete Filter for EEG Application on FPGA , 2018 .

[3]  Ajith A. Pasqual,et al.  A generalized preprocessing and feature extraction platform for scalp EEG signals on FPGA , 2014, 2014 IEEE Conference on Biomedical Engineering and Sciences (IECBES).

[4]  Naveen Verma,et al.  A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System , 2010, IEEE Journal of Solid-State Circuits.

[5]  David A. Johns,et al.  Design and analysis of delta-sigma based IIR filters , 1993 .

[6]  Pradeepa,et al.  FPGA based filters for EEG pre-processing , 2016, 2016 Second International Conference on Science Technology Engineering and Management (ICONSTEM).

[7]  A. Miri,et al.  Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic , 2006, 2006 IEEE International Symposium on Signal Processing and Information Technology.

[8]  Shumit Saha,et al.  FPGA implementation of modified type-C PID control system , 2015, 2015 International Conference on Electrical Engineering and Information Communication Technology (ICEEICT).

[9]  Md. Tariq Hasan,et al.  FPGA implementation of LBlock lightweight block cipher , 2016, 2016 3rd International Conference on Electrical Engineering and Information Communication Technology (ICEEICT).

[10]  Atik Mahabub Design and Implementation of Cost-effective Simple FIR Filter for EEG Signal on FPGA , 2019 .

[11]  G.D. Cain,et al.  Approximation of FIR by IIR digital filters: an algorithm based on balanced model reduction , 1992, IEEE Trans. Signal Process..

[12]  Shumit Saha,et al.  Dynamically reconfigurable parallel architecture implementation of 2D convolution for image processing over FPGA , 2015, 2015 International Conference on Electrical Engineering and Information Communication Technology (ICEEICT).

[13]  M. Vignesh,et al.  FPGA implementation of fast running FIR filters , 2017, 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET).

[14]  Po-Lei Lee,et al.  Development of a Low-Cost FPGA-Based SSVEP BCI Multimedia Control System , 2010, IEEE Transactions on Biomedical Circuits and Systems.

[15]  Joseph B. Evans Efficient FIR filter architectures suitable for FPGA implementation , 1994 .