An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS

An interference-robust reconfigurable receiver in 65-nm CMOS is presented. The front end is split into a low-band (LB) RF path (0.1–1.5 GHz) and a high-band (HB) RF path (1–5 GHz). By utilizing a harmonic recombination technique, the LB path could reject the third /fifth-order harmonic interferences. A tunable narrowband dual-feedback common-gate low-noise amplifier (LNA) with $LC$ resonant load provides second-order bandpass filtering to reject the harmonic interferences in the HB path. The RF high-Q bandpass filtering based on the voltage-mode passive mixer and the current-mode low-pass filter in the analog baseband improves the receiver’s resilience to out-of-band interferences. A novel power-detection-based automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations. The presented receiver has been implemented in a 65-nm CMOS and consumes 20–76-mW power from 1.2-V power supplies, with a core die area of 5 mm2. The measured results show that the receiver can tolerate −5-dBm interference with 16-dB noise figure (NF) and achieve 95–105-dB maximum conversion gain and 1.7–8-dB NF over 0.1–5 GHz. It also achieves an average harmonic rejection (HR3)/HR5 of 61/68-dB, +7.1/+14.4 dBm in-band/out-of-band input third-order intercept point (OB-IIP3), +71.2-dBm OB-IIP2, and 58.1-dB-image rejection, after the digitally assisted calibrations. The system-level measurements show that the presented receiver achieves 2.1% error vector magnitude (EVM) for 850-MHz Global System for Mobile Communication signals and 5% EVM for band 42 time division duplexing-local thermal equilibrium (LTE) signals, respectively.

[1]  James F. Buckwalter,et al.  A 0.4–6-GHz 17-dBm B1dB 36-dBm IIP3 Channel-Selecting Low-Noise Amplifier for SAW-Less 3G/4G FDD Diversity Receivers , 2016, IEEE Transactions on Microwave Theory and Techniques.

[2]  Zhihua Wang,et al.  A 0.1-5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS , 2018, Microelectron. J..

[3]  Rinaldo Castello,et al.  SAW-less analog front-end receivers for TDD and FDD , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  Howard C. Luong,et al.  A 0.9GHz–5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio , 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

[5]  Hossein Hashemi,et al.  A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing , 2014, IEEE Journal of Solid-State Circuits.

[6]  Eric A. M. Klumperink,et al.  A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  Hossein Hashemi,et al.  Reconfigurable Receiver With Radio-Frequency Current-Mode Complex Signal Processing Supporting Carrier Aggregation , 2015, IEEE Journal of Solid-State Circuits.

[8]  Alyosha C. Molnar,et al.  A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface , 2010, IEEE Journal of Solid-State Circuits.

[9]  Jonathan Borremans,et al.  A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration , 2014, IEEE Journal of Solid-State Circuits.

[10]  Jonathan Borremans,et al.  A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers , 2011, IEEE Journal of Solid-State Circuits.

[11]  Byeong-Ha Park,et al.  A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[12]  David Murphy,et al.  A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers , 2015, IEEE Journal of Solid-State Circuits.

[13]  Namsoo Kim,et al.  A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[14]  Zhihua Wang,et al.  An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS , 2015, Microelectron. J..

[15]  David J. Allstot,et al.  A capacitor cross-coupled common-gate low-noise amplifier , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  Liang Wu,et al.  A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Donggu Im,et al.  A CMOS Resistive Feedback Differential Low-Noise Amplifier With Enhanced Loop Gain for Digital TV Tuner Applications , 2009, IEEE Transactions on Microwave Theory and Techniques.

[18]  Hossein Hashemi,et al.  A 50 MHz–6 GHz, 2 × 2 MIMO, reconfigurable architecture, software-defined radio in 130nm CMOS , 2014, 2014 IEEE Radio Frequency Integrated Circuits Symposium.