A Combined Architecture for FDCT Algorithm

A single generalized architecture has been deviced which can perform 4 FDCT algorithms namely, Arai's, Chen's, Loeffler's and Vetterli's by varying the control signals. Simulink files containing block design files of 4 FDCT algorithms are included. From the Simulink file appropriate language (VHDL) for the target board (FPGA) can be generated. The VHDL code is run in MODELSIM XE III/Starter 6.1e-custom Xilinx Version. Here the target board is XILINX VIRTEX-IV PRO. The obtained results are compared and concluded.

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