Accelerating Heap-Based Priority Queue in Image Coding Application Using Parallel Index-Aware Tree Access

We present a novel heap-based priority queue structure for hardware implementation which is employed by a wavelet-based image encoder. The architecture exploits efficient use of FPGA’s on-chip dual port memories in an adaptive manner. By using 2x clock speed we created 4 memory ports along with intelligent data concatenation of parents and children queue elements, as well as an index-aware system linked to each key in the queue. These innovations yielded in cost effective enhanced memory access. The memory ports are adaptively assigned to different units during different computation phases of operations in a manner to optimally take advantage of memory access required by that phase. We designed this architecture to incorporate in our Adaptive Scanning of Wavelet Data (ASWD) module which reorganizes the wavelet coefficients into locally stationary sequences for a wavelet-based image encoder. We validated the hardware on an Altera’s Stratix IV FPGA as an IP accelerator in a Nios II processor based System on Chip. The architectural innovations can also be exploited in other applications that require efficient hardware implementations of priority queue. We show that our architecture at 150MHz can provide 45X speedup compared to an embedded ARM Cortex-A9 processor at 666MHz.