Resistor-capacitor reinforcement-based memory cell of static random access memory

The invention provides a resistor-capacitor reinforcement based memory cell of a static random access memory. The memory cell comprises a latch circuit and a bit selection circuit. The latch circuit is composed of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistor-capacitor network and a second resistor-capacitor network; the bit selection circuit is composed of NMOS transistors N5 and N6; the latch circuit forms four storage points X1, X1B, X2 and X2B, and a coupling capacitor C is arranged between one complementary pair of the data storage points. Compared with a traditional 6T structure memory cell, the memory cell is additionally provided with the resistor-capacitor networks and the coupling capacitor. Under the conditions that the original read operation path is not changed and the complexity is not obviously increased, the memory cell is prevented from single event upsets at the cost of a little increment in area, thereby ensuring the correctness of data.