3차원으로 적층된 수직형 NAND 플래시 메모리 특성 분석

The characteristic of vertical NAND flash memory cell array is investigated by numerical simulation. The gap size between word lines should be reduced for bit line current drivability. Also, channel hole size is the critical parameter that determine program speed. These results will be the important issues of the 3D stacked vertical NAND array for reliable memory operation.