Exploring DRAM organizations for energy-efficient and resilient exascale memories
暂无分享,去创建一个
David Blaauw | Ronald G. Dreslinski | Chaitali Chakrabarti | Trevor N. Mudge | Bharan Giridhar | Robert Patti | Hsing Min Chen | Betina Hold | Michael Cieslak | Deepankar Duggal | T. Mudge | R. Dreslinski | D. Blaauw | C. Chakrabarti | R. Patti | Bharan Giridhar | H. Chen | Michael Cieslak | Deepankar Duggal | B. Hold
[1] Norman P. Jouppi,et al. Rethinking DRAM design and organization for energy-constrained multi-cores , 2010, ISCA.
[2] Doe Hyun Yoon,et al. Virtualized ECC: Flexible Reliability in Main Memory , 2011, IEEE Micro.
[3] Bianca Schroeder,et al. Cosmic rays don't strike twice: understanding the nature of DRAM errors and the implications for system design , 2012, ASPLOS XVII.
[4] Harish Patil,et al. Pin: building customized program analysis tools with dynamic instrumentation , 2005, PLDI '05.
[5] David Blaauw,et al. Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.
[6] Franck Cappello,et al. Toward Exascale Resilience , 2009, Int. J. High Perform. Comput. Appl..
[7] Onur Mutlu,et al. A case for exploiting subarray-level parallelism (SALP) in DRAM , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[8] Onur Mutlu,et al. Tiered-latency DRAM: A low latency and low cost DRAM architecture , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).
[9] Christoforos E. Kozyrakis,et al. Future scaling of processor-memory interfaces , 2009, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis.
[10] Ke Chen,et al. System implications of memory reliability in exascale computing , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).
[11] Babak Falsafi,et al. Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[12] L. Borucki,et al. Comparison of accelerated DRAM soft error rates measured at component and system level , 2008, 2008 IEEE International Reliability Physics Symposium.
[13] Timothy J. Dell,et al. A white paper on the benefits of chipkill-correct ecc for pc server main memory , 1997 .
[14] Luca Benini,et al. Exploration and Optimization of 3-D Integrated DRAM Subsystems , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Eduardo Pinheiro,et al. DRAM errors in the wild: a large-scale field study , 2009, SIGMETRICS '09.
[16] Song Huang,et al. On the energy efficiency of graphics processing units for scientific computing , 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.
[17] Mark Anders,et al. Near-threshold voltage (NTV) design — Opportunities and challenges , 2012, DAC Design Automation Conference 2012.
[18] Jung Ho Ahn,et al. Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs , 2009, IEEE Computer Architecture Letters.
[19] Krisztián Flautner,et al. PicoServer: Using 3D stacking technology to build energy efficient servers , 2008, JETC.
[20] Jeffrey S. Vetter. On the road to Exascale: lessons from contemporary scalable GPU systems , 2012, HiPC 2012.
[21] Christoforos E. Kozyrakis,et al. Improving System Energy Efficiency with Memory Rank Subsetting , 2012, TACO.
[22] Gabriel H. Loh,et al. 3D-Stacked Memory Architectures for Multi-core Processors , 2008, 2008 International Symposium on Computer Architecture.
[23] Young-Hyun Jun,et al. A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking , 2011, IEEE Journal of Solid-State Circuits.
[24] Richard Veras,et al. RAIDR: Retention-aware intelligent DRAM refresh , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[25] Dong Tang,et al. Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults , 2006, International Conference on Dependable Systems and Networks (DSN'06).
[26] Zhao Zhang,et al. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[27] Eiji Fujiwara,et al. Error-control coding for computer systems , 1989 .
[28] George Bosilca,et al. Open MPI: Goals, Concept, and Design of a Next Generation MPI Implementation , 2004, PVM/MPI.
[29] Vivek Sarkar,et al. Software challenges in extreme scale systems , 2009 .
[30] Hsien-Hsin S. Lee,et al. Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[31] Tryggve Fossum,et al. Cache scrubbing in microprocessors: myth or necessity? , 2004, 10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings..
[32] Goichi Ono,et al. A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process , 2010, IEEE Journal of Solid-State Circuits.
[33] Lewis Winner,et al. 1972 IEEE International Solid-State Circuits Conference : digest of technical papers : ISSCC , 1969 .
[34] Michael C. Huang,et al. An empirical study of memory hardware errors in a server farm , 2007 .
[35] Vilas Sridharan,et al. A study of DRAM failures in the field , 2012, 2012 International Conference for High Performance Computing, Networking, Storage and Analysis.
[36] Young-Hyun Jun,et al. A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking , 2011, 2011 IEEE International Solid-State Circuits Conference.
[37] Jung-Bae Lee,et al. A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme , 2012, 2012 IEEE International Solid-State Circuits Conference.