Mechanically flexible interconnects (MFIs) with highly scalable pitch

Mechanically flexible interconnects (MFIs) with highly scalable pitch (from 150 to 50 µm) and large vertical gap (65 µm) are reported for the first time in this paper. The wafer-level batch fabrication of the reported MFIs is enabled by photolithography on a highly non-uniform surface (65 µm high sacrificial domes) covered with a spray-coated photoresist. Based on finite element method simulations and experimental data, the mechanical compliance and resistance of the fabricated MFIs are reported.

[1]  Qi Zhu,et al.  J-Springs - innovative compliant interconnects for next-generation packaging , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[2]  R. Ho,et al.  Novel packaging with rematable spring interconnect chips for MCM , 2009, 2009 59th Electronic Components and Technology Conference.

[3]  U. Schnakenberg,et al.  Electrodeposition and properties of NiW films for MEMS application , 2005 .

[4]  K. Kacker,et al.  FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[5]  Suresh K. Sitaraman,et al.  Three-path electroplated copper compliant interconnects — Fabrication and modeling studies , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[6]  Muhannad S. Bakir,et al.  Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI) , 2003 .

[7]  Young Chul Kim,et al.  fcCuBE technology: A pathway to advanced Si-node and fine pitch flip chip , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[8]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[9]  R. Chaware,et al.  Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[10]  Dongwook Kim,et al.  Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV) , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[11]  John H. Lau,et al.  Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects , 2009, 2009 59th Electronic Components and Technology Conference.

[12]  M. Bakir,et al.  Design, Fabrication, and Characterization of Freestanding Mechanically Flexible Interconnects Using Curved Sacrificial Layer , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[13]  M. Bakir,et al.  Highly Elastic Gold Passivated Mechanically Flexible Interconnects , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[15]  S. Muthukumar,et al.  High-density compliant die-package interconnects , 2006, 56th Electronic Components and Technology Conference 2006.