A 4-Bit, 1.6 GS/s Low Power Flash ADC, Based on Offset Calibration and Segmentation

A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after calibration. The converter offers 3.8 effective number of bits (ENOB) at 1.6 GS/s sampling rate with a low frequency input signal and more than 1.8 GHz effective resolution bandwidth (ERBW) at this sampling rate. The converter consumes mere 15.5 mW from a 1.8 V supply, yielding an FoM of 695 fJ/conversion.step and occupies 0.3 mm2 in a 0.18 μm standard CMOS process.

[1]  Jin Liu,et al.  Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Michel Steyaert,et al.  A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[3]  Marios C. Papaefthymiou,et al.  A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[4]  Atila Alvandpour,et al.  A CMOS comparator with reduced kick-back for a 4-6-bit 3-GS/S flash ADC in a 90NM process. , 2007 .

[5]  Pedro M. Figueiredo,et al.  Averaging technique in flash analog-to-digital converters , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Shahriar Mirabbasi,et al.  A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[7]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[8]  Pierangelo Terreni,et al.  A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18 um CMOS with 5.8GHz ERBW , 2006 .

[9]  J.G. Peterson,et al.  A monolithic video A/D converter , 1979, IEEE Journal of Solid-State Circuits.

[10]  Ehsan Afshari,et al.  A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[11]  Jan Craninckx,et al.  A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS , 2009, IEEE Journal of Solid-State Circuits.

[12]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[13]  G. Van der Plas,et al.  A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS , 2008, 2008 IEEE Symposium on VLSI Circuits.

[14]  Teresa H. Meng,et al.  Power-efficient metastability error reduction in CMOS flash A/D converters , 1995 .

[15]  M El-Chammas,et al.  A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration , 2011, IEEE Journal of Solid-State Circuits.

[16]  T. Miki,et al.  A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[17]  F. Kuttner,et al.  A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.

[18]  Denis C. Daly,et al.  A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy , 2009, IEEE Journal of Solid-State Circuits.

[19]  Kwang Young Kim,et al.  A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration , 2008, IEEE Journal of Solid-State Circuits.

[20]  I. Mehr,et al.  A 500 msample/s 6–bit Nyquist rate ADC for disk drive read channel applications , 1998 .

[21]  Hui Pan,et al.  Spatial filtering in flash A/D converters , 2003 .

[22]  Zhiwei Xu,et al.  A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[23]  Atila Alvandpour,et al.  Utilizing Process Variations for Reference Generation in a Flash ADC , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[24]  Tomohiko Ito,et al.  A 3-GS/s 5-bit 36-mW flash ADC in 65-nm CMOS , 2010, 2010 IEEE Asian Solid-State Circuits Conference.