Defect-oriented Verilog fault simulation of SoC macros using a stratified fault sampling technique

The validation of high-quality tests requires defect-oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO Verilog fault simulation. A novel tool, veriDOF, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults, using a pre-computed test view of each library cell. A stratified fault sampling technique is used to boost the computational efficiency of the new tool. Results are presented for ISCAS benchmarks and a public domain processor, PIC.

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