A concurrent trace debugging method for multi-core chip based on generic algorithm

Trace-based debugging technologies need connect trace signals to trace buffer with additional infrastructure, which not only consumes the limited on chip resource, but also results in the problem of signal integration. Reusing network-on-chip eliminates the problems. But it is still a challenge problem that how to determine the locations of trace buffer under the limitations of link bandwidth and transmission power. We formulate it as P-Median problem which is NP-hard. Then a method based on generic algorithm is proposed. It can optimize the location number of trace buffers and transmission power simultaneously. Experimental results show that multiple trace buffer locations can increase the number of concurrent trace signals in contrast to centralized trace buffer. Compared to previous method, the proposed method can deducing the locations of trace buffer and reducing the transmission power efficiently.