Air-gap/SiO2 liner TSVs with improved electrical performance

This paper reports fabrication and characterization of TSVs that use combined air-gap/SiO2 as the insulators. Fabrication technologies based on reactive ion etching (RIE) of benzocyclobutene (BCB) sacrificial layers have been developed to fabricate uniform and high aspect-ratio air-gaps, and air-gaps with thickness of 2 μm and aspect-ratio of 25:1 have been successfully fabricated. The measured capacitance-voltage (C-V) and current-voltage (I-V) curves at room temperature and high temperatures show that the TSVs with air-gap/SiO2 liners have low capacitance and leakage current. Compared with the TSVs using a sole air-gap insulator, the additional SiO2 liners protects the TSV from being influenced by the residues of sacrificial materials, and the electrical performance and thermal stability are improved.

[1]  Suk-kyu Ryu,et al.  Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration , 2012, IEEE Transactions on Device and Materials Reliability.

[2]  A. Jourdain,et al.  Temperature dependent electrical characteristics of through-si-via (TSV) interconnections , 2010, 2010 IEEE International Interconnect Technology Conference.

[3]  R. Bashirullah,et al.  Design and fabrication of low-loss horizontal and vertical interconnect links using air-clad transmission lines and through silicon vias , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[4]  Luca Benini,et al.  Design Issues and Considerations for Low-Cost 3-D TSV IC Technology , 2010, IEEE Journal of Solid-State Circuits.

[5]  Bart Vandevelde,et al.  Cu pumping in TSVs: Effect of pre-CMP thermal budget , 2011, Microelectron. Reliab..

[6]  Eric Beyne,et al.  A novel concept for ultra-low capacitance via-last TSV , 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

[7]  D. Henry,et al.  Process solutions and polymer materials for 3D-WLP through silicon via filling , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[8]  W. Dehaene,et al.  Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance , 2010, IEEE Electron Device Letters.

[9]  Junho Lee,et al.  High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV) , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[10]  John H. Lau,et al.  Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[11]  Zheyao Wang,et al.  Implementation of Air-Gap Through-Silicon-Vias (TSVs) Using Sacrificial Technology , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[12]  Zheyao Wang,et al.  Thermal and Electrical Reliability Tests of Air-Gap Through-Silicon Vias , 2015, IEEE Transactions on Device and Materials Reliability.

[13]  C. Okoro,et al.  A Detailed Failure Analysis Examination of the Effect of Thermal Cycling on Cu TSV Reliability , 2014, IEEE Transactions on Electron Devices.

[14]  E. Beyne,et al.  Technology Assessment of Through-Silicon Via by Using $C$–$V$ and $C$– , 2011, IEEE Electron Device Letters.

[15]  Suk-kyu Ryu,et al.  Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects , 2011, IEEE Transactions on Device and Materials Reliability.

[16]  E. Beyne,et al.  3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[17]  Zheyao Wang,et al.  Benzocyclobutene polymer filling of high aspect-ratio annular trenches for fabrication of Through-Silicon-Vias (TSVs) , 2012, Microelectron. Reliab..

[18]  E. Beyne,et al.  Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[19]  Zheng Xu,et al.  Through-Silicon-Via Fabrication Technologies, Passives Extraction, and Electrical Modeling for 3-D Integration/Packaging , 2013, IEEE Transactions on Semiconductor Manufacturing.

[20]  M. Sunohara,et al.  Studies on electrical performance and thermal stress of a silicon interposer with TSVs , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[21]  L. Zhang,et al.  Achieving Stable Through-Silicon Via (TSV) Capacitance with Oxide Fixed Charge , 2011, IEEE Electron Device Letters.

[22]  Zheyao Wang,et al.  Ultralow-Capacitance Through-Silicon Vias With Annular Air-Gap Insulation Layers , 2013, IEEE Transactions on Electron Devices.