Analysis of the Performance Impact on Dynamic Comparator for Analog to Digital Converter Under Process Mismatch

In recent years, with the progress of the CMOS process technology, the speed of transistor has increased dramatically. Thus, the speed of Analog-to-Digital Converter (ADC) also improved, even up to the frequency of GHz. In Analog-to-Digital Converter, the dynamic comparator and sample-and-hold circuit are generally used. In this paper, the Monte Carlo method is used to analyze the performance impact of the dynamic comparator under process mismatches and to examine the yield of dynamic comparator over different voltage differences. This analysis method can be applied to dynamic comparators of high-speed analog-to-digital converters, such as flash ADC and successive-approximation ADC.