8-bit AES FPGA Implementation using Block RAM
暂无分享,去创建一个
[1] Akashi Satoh,et al. A Compact Rijndael Hardware Architecture with S-Box Optimization , 2001, ASIACRYPT.
[2] Ingrid Verbauwhede,et al. Minimum area cost for a 30 to 70 Gbits/s AES processor , 2004, IEEE Computer Society Annual Symposium on VLSI.
[3] Keshab K. Parhi,et al. High-speed VLSI architectures for the AES algorithm , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] Kris Gaj,et al. Very Compact FPGA Implementation of the AES Algorithm , 2003, CHES.
[5] Stamatis Vassiliadis,et al. Reconfigurable memory based AES co-processor , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.
[6] Tim Good,et al. Very small FPGA application-specific instruction processor for AES , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.
[7] Jean-Didier Legat,et al. Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..