A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-cou...

[1]  Jae-Won Nam,et al.  A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation , 2018, IEEE Journal of Solid-State Circuits.

[2]  Wei-Hsin Tseng,et al.  A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters , 2016, IEEE Journal of Solid-State Circuits.

[3]  Tsung-Han Tsai,et al.  An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Xin Xin,et al.  Ultra-low power comparator with dynamic offset cancellation for SAR ADC , 2017 .

[5]  Ramesh Harjani,et al.  A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Soon-Jyh Chang,et al.  10-bit 30-MS/s SAR ADC Using a Switchback Switching Method , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Kai Tang,et al.  A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Zhang Jun-an,et al.  A 10-bit 1.2 GS/s 45 mW time-interleaved SAR ADC with background calibration , 2018, IEICE Electron. Express.

[9]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[10]  Qiang Li,et al.  High-speed low-power common-mode insensitive dynamic comparator , 2015 .

[11]  Fan Ye,et al.  Settling optimised sample-and-hold circuit with high-linearity input switch in 65 nm CMOS , 2010 .

[12]  Hae-Seung Lee,et al.  A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration , 2014, IEEE Journal of Solid-State Circuits.

[13]  Tao Liu,et al.  A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Po-Chiun Huang,et al.  A 0.003 mm$^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching , 2015, IEEE Journal of Solid-State Circuits.

[15]  Qiang Li,et al.  Design Considerations of Ultralow-Voltage Self-Calibrated SAR ADC , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  Boris Murmann,et al.  An 8-bit 450-MS/s single-bit/cycle SAR ADC in 65-nm CMOS , 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

[17]  Qiang Li,et al.  A monotonic SAR ADC with system-level error correction , 2015 .

[18]  Yun Chiu,et al.  A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer , 2017, IEEE Journal of Solid-State Circuits.

[19]  Yintang Yang,et al.  A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[20]  Yu-Hsuan Tu,et al.  A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC , 2016, IEEE Journal of Solid-State Circuits.

[21]  Wan Kim,et al.  A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC , 2016, IEEE Journal of Solid-State Circuits.

[22]  Ameya Bhide,et al.  A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-$\mu$m CMOS for Medical Implant Devices , 2012, IEEE Journal of Solid-State Circuits.

[23]  Guangbing Chen,et al.  High-speed low-power and low-power supply voltage dynamic comparator , 2015 .