All-digital PLL array provides reliable distributed clock for SOCs

This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method.

[1]  Gordon W. Roberts,et al.  A high-resolution flash time-to-digital converter and calibration scheme , 2004, 2004 International Conferce on Test.

[2]  Gill A. Pratt,et al.  Distributed Synchronous Clocking , 1995, IEEE Trans. Parallel Distributed Syst..

[3]  M. Sasaki.  A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators , 2009, IEEE Journal of Solid-State Circuits.

[4]  G. Scorletti,et al.  An LMI approach to dencentralized H8 control , 2001 .

[5]  S. Tam,et al.  A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache , 2007, IEEE Journal of Solid-State Circuits.

[6]  A.P. Chandrakasan,et al.  Active GHz clock network using distributed PLLs , 2000, IEEE Journal of Solid-State Circuits.

[7]  N. Kurd,et al.  Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking , 2009, IEEE Journal of Solid-State Circuits.

[8]  J.A. Tierno,et al.  A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI , 2008, IEEE Journal of Solid-State Circuits.

[9]  Jérôme Juillard,et al.  A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[10]  Liu Hongxia,et al.  An LMI Approach to Decentralized H_∞-Controller Design of a Class of Uncertain Large-Scale Interconnected Time-Delay Systems , 2001 .

[11]  J. Juillard,et al.  Design and VHDL modeling of all-digital PLLs , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.