Design system for vlsi chip on carrier, and module designed with it

PURPOSE: To attain optimum shortening of the entire length of connection wires, by integrating a super large scale integrated package in a design system at an initial stage so that a chip boundary is suppressed more or less, for a reduced operation of division area. CONSTITUTION: A minimum numbers of input/output contact points (I/O) between chips 111-11n, 121-12n, 131-13n, 141-14n, 211-21n, 221-22n, 231-23n, 241-24n are provided. I/O (A0 to A0, A1 to A1, An to An, 121 to 221, 131 to 231, 141 to 241) corresponding to different chips 1X, 2X, 1, and 2 are assigned facing between others. Circuits belonging to I/O (C0-Cn, D0-Dn, E0-En) and related to them are assigned in division areas 50, 60, and 70 of each chip 3x while setting close to I/O as much as possible. Thus, an overall yield wherein all electric circuits are optimized with shortest entire connection wire length is provided. COPYRIGHT: (C)1991,JPO