Clock and Data Recovery Circuits

[1]  G. Gutierrez,et al.  2.488 Gb/s silicon bipolar clock and data recovery IC for SONET (OC-48) , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[2]  Azita Emami-Neyestanak,et al.  A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Ali Hajimiri,et al.  Concepts and methods in optimization of integrated LC VCOs , 2001, IEEE J. Solid State Circuits.

[4]  Martin L. Schmatz,et al.  A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  Behzad Razavi,et al.  A study of oscillator jitter due to supply and substrate noise , 1999 .

[6]  Aaron Wayne Buchwald Design of Integrated Fiber-Optic Receivers Using Heterojunction Bipolar Transistors. , 1993 .

[7]  B. Razavi Monolithic phase-locked loops and clock recovery circuits : theory and design , 1996 .

[8]  B. Razavi,et al.  A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector , 2001, IEEE J. Solid State Circuits.

[9]  Pavan Kumar Hanumolu,et al.  A 1.6Gbps Digital Clock and Data Recovery Circuit , 2006, IEEE Custom Integrated Circuits Conference 2006.

[10]  A. Hajimiri,et al.  Design issues in CMOS differential LC oscillators , 1999, IEEE J. Solid State Circuits.

[11]  J.D.H. Alexander Clock recovery from random binary signals , 1975 .

[12]  Adrian Maxim,et al.  Notice of Violation of IEEE Publication PrinciplesA Varactor-Less 10GHz CMOS LC-VCO for Optical Communications Transceiver SOCs Using Caged Inductors , 2006, IEEE Custom Integrated Circuits Conference 2006.

[13]  Albrecht Rothermel,et al.  Clock/data recovery PLL using half-frequency clock , 1997 .

[14]  B. Razavi,et al.  Analysis and modeling of bang-bang clock and data recovery circuits , 2004, IEEE Journal of Solid-State Circuits.

[15]  William J. Dally,et al.  A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[16]  E. Hegazi,et al.  23.4 A Filtering Technique to Lower Oscillator Phase Noise , 2008 .

[17]  Behzad Razavi,et al.  A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.

[18]  J.C. Leete,et al.  A 2.4 GHz CMOS transceiver for Bluetooth , 2001, 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173).

[19]  J.C. Scheytt,et al.  A 0.155, 0.622, and 2.488 Gb/s automatic bit rate selecting clock and data recovery IC for bit rate transparent SDH-systems , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[20]  Frank Ellinger,et al.  A 25Gb/s CDR in 90nm CMOS for High-Density Interconnects , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[21]  F. Ellinger,et al.  A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects , 2006, IEEE Journal of Solid-State Circuits.

[22]  J. L. Sonntag,et al.  A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links , 2006 .

[23]  D. Friedman,et al.  A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[24]  C.R. Hogge A self correcting clock recovery circuit , 1985, IEEE Transactions on Electron Devices.

[25]  A. Abidi,et al.  Physical processes of phase noise in differential LC oscillators , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[26]  G.L. Fredendall,et al.  Automatic Frequency and Phase Control of Synchronization in Television Receivers , 1943, Proceedings of the IRE.

[27]  Jri Lee,et al.  A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[28]  D. Inglis,et al.  A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs , 2002, IEEE Journal of Solid-State Circuits.

[29]  John A. McNeill Jitter in ring oscillators , 1997 .