2.6 GHz receiver for on-chip optical networking in 65nm CMOS technology

This paper presents a 2.6 GHz optical receiver with full rail-to-rail output swing, designed in the ST 65 nm CMOS technology for the hybrid integration with a III–IV photodetector. The receiver consists of a 1 kΩ transimpedance amplifier (TIA) followed by a postamplifier based on a biased common source chain. The bias circuits allow for improving the robustness of the system against supply voltage fluctuations and temperature variations. The receiver has a simulated resolution of 2 µApp at 4 Gb/s, with an input capacitance of 0.1 pF, and draws approximately 2.6 mW from the 1 V supply. An instantaneous response multiple decision thresholds output stage is also proposed for overcoming the limitation of an automatic offset control circuit1.

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