SEU-induced persistent error propagation in FPGAs

This paper introduces a new way to characterize the dynamic single-event upset (SEU) cross section of an FPGA design in terms of its persistent and nonpersistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the nonpersistent cross section causes a temporary interruption of service. These cross sections have been measured for several designs using fault-injection and proton testing. Some FPGA applications may realize increased reliability at lower costs by focusing SEU mitigation on just the persistent cross section.

[1]  Michael E. Brown,et al.  Introduction to Space Physics , 1995 .

[2]  Andrew Holmes-Siedle,et al.  Handbook of Radiation Effects , 1993 .

[3]  Kenneth A. LaBel,et al.  Radiation effects on current field programmable technologies , 1997 .

[4]  E. Petersen,et al.  Cross section measurements and upset rate calculations , 1996 .

[5]  C. Carmichael,et al.  Proton Testing of SEU Mitigation Methods for the Virtex FPGA , 2001 .

[6]  Michael J. Wirthlin,et al.  Predicting On-Orbit SEU Rates , 2005 .

[7]  Michael J. Wirthlin,et al.  Correlation of Fault-Injection to Proton Accelerator Persistent Cross Section Measurements , 2005 .

[8]  F. W. Sexton,et al.  Modeling the heavy ion upset cross section , 1995 .

[9]  S. Mahammad,et al.  Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGAs , 2005 .

[10]  P. Sundararajan,et al.  Testing FPGA Devices Using JBits , 2001 .

[11]  Jih-Jong Wang,et al.  SRAM based re-programmable FPGA for space applications , 1999 .

[12]  T. L. Turflinger,et al.  Understanding single event phenomena in complex analog and digital integrated circuits , 1990 .

[13]  Michael J. Wirthlin,et al.  Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets , 2002 .

[14]  R. Koga,et al.  Techniques of Microprocessor Testing and SEU-Rate Prediction , 1985, IEEE Transactions on Nuclear Science.

[15]  M. Caffrey,et al.  Evaluating TMR Techniques in the Presence of Single Event Upsets , 2003 .

[16]  M. Wirthlin,et al.  Improving FPGA Design Robustness with Partial TMR , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[17]  Michael J. Wirthlin,et al.  The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[18]  Fabian Vargas,et al.  Improving Reconfigurable Systems Reliability by Combining Periodical Test and Redundancy Techniques: A Case Study , 2001, J. Electron. Test..

[19]  M. Caffrey,et al.  Correcting single-event upsets through virtex partial configuration , 2000 .

[20]  J. C. Pickel,et al.  Rate prediction for single event effects-a critique , 1992 .

[21]  N. Cohen,et al.  Soft error considerations for deep-submicron CMOS circuit applications , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[22]  C. Carmichael,et al.  A fault injection analysis of Virtex FPGA TMR design methodology , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).

[23]  Mehdi Baradaran Tahoori,et al.  Soft error rate estimation and mitigation for SRAM-based FPGAs , 2005, FPGA '05.

[24]  Paul Graham,et al.  Accelerator validation of an FPGA SEU simulator , 2003 .

[25]  Anthony Salazar,et al.  Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing , 1999 .

[26]  R. Koga,et al.  Single ion induced multiple-bit upset in IDT 256K SRAMs , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).

[27]  Alessandro Paccagnella,et al.  Ion beam testing of ALTERA APEX FPGAs , 2002, IEEE Radiation Effects Data Workshop.

[28]  M. Wirthlin,et al.  Reconfigurable computing in space: from current technology to reconfigurable systems-on-a-chip , 2003, 2003 IEEE Aerospace Conference Proceedings (Cat. No.03TH8652).

[29]  Michael J. Wirthlin,et al.  SEU mitigation for half-latches in Xilinx Virtex FPGAs , 2003 .

[30]  E. Fuller,et al.  RADIATION TESTING UPDATE, SEU MITIGATION, AND AVAILABILITY ANALYSIS OF THE VIRTEX FPGA FOR SPACE RECONFIGURABLE COMPUTING. , 2000 .

[31]  G. M. Swift,et al.  Single-event upset test results for the Xilinx XQ1701L PROM , 1999, 1999 IEEE Radiation Effects Data Workshop. Workshop Record. Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference (Cat. No.99TH8463).

[32]  M. Caffrey,et al.  Detection of Configuration Memory Upsets Causing Persistent Errors in SRAM-based FPGAs , 2004 .

[33]  G. M. Swift,et al.  In-flight observations of multiple-bit upset in DRAMs , 2000 .

[34]  C. Carmichael,et al.  Single event upset suspectibility testing of the Xilinx Virtex II FPGA , 2002 .

[35]  R. Katz,et al.  Current radiation issues for programmable elements and devices , 1998 .

[36]  Carl Carmichael,et al.  Triple Module Redundancy Design Techniques for Virtex FPGAs, Application Note 197 , 2001 .

[37]  C. Carmichael,et al.  Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions , 2004, IEEE Transactions on Nuclear Science.

[38]  Darrel E. Johnson,et al.  Estimating the Dynamic Sensitive Cross Section of an FPGA Design through Fault injection , 2005 .

[39]  C. Carmichael,et al.  Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs) , 2004, IEEE Transactions on Nuclear Science.