Performance Enhancement of Full Adder Circuit: Current Mode Operated Majority Function Based Design
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[1] Tarek Darwish,et al. Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[2] Bradley A. Minch. Low-Voltage Wilson Current Mirrors in CMOS , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[3] Wolfgang Fichtner,et al. Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.
[4] Aminul Islam,et al. Performance evaluation of MCML-based XOR/XNOR circuit at 16-nm Technology node , 2014, 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies.
[5] D. G. Haigh,et al. Design and application of GaAs MESFET current mirror circuits , 1990 .
[6] B. Wilson,et al. Recent developments in current conveyors and current-mode circuits , 1990 .
[7] Aminul Islam,et al. Robust subthreshold full adder design technique , 2011, 2011 International Conference on Multimedia, Signal Processing and Communication Technologies.
[8] Ehsan Mazidi. Designing current mirror with Nano wire FET , 2010, 2010 IEEE Nanotechnology Materials and Devices Conference.
[9] Aminul Islam,et al. A comparative analysis of various programmable delay elements using predictive technology model , 2016, 2016 International Conference on Microelectronics, Computing and Communications (MicroCom).
[10] Aminul Islam,et al. Nonvolatile and Robust Design of Content Addressable Memory Cell Using Magnetic Tunnel Junction at Nanoscale Regime , 2015, IEEE Transactions on Magnetics.
[11] E. Abu-Shama,et al. A new cell for low power adders , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[12] Yin-Tsung Hwang,et al. A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.