A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard

The Advanced Encryption Standard, which is used extensively for secure communications, has been accepted recently as a symmetric cryptography standard. However, occurrence of the internal faults by intrusion of the attackers may cause confidential information leak to reveal the secret key. For this reason, several schemes for fault detection of the transformations and rounds in the encryption and decryption of the Advanced Encryption Standard are proposed. In this paper, we present a structure-independent fault detection scheme for the Advanced Encryption Standard. The proposed scheme is independent of the way S- box (inverse S-box) is constructed and can be used for both encryption and decryption. It can be applied to both the S-boxes (and inverse S-boxes) using look-up tables as well as those utilizing logic gate implementations based on composite fields. We have obtained the formulations for the fault detection of the SubBytes (inverse SubBytes) using the relation between the input and output of the S-box (inverse S-box). Then, we have proposed and simulated a signature-based structure-independent fault detection scheme. Moreover, the FPGA implementations of the original and the proposed schemes as well as their overhead are presented.

[1]  Mark G. Karpovsky,et al.  Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard , 2004, CARDIS.

[2]  Johannes Blömer,et al.  Fault Based Collision Attacks on AES , 2006, FDTC.

[3]  Bing-Fei Wu,et al.  Simple error detection methods for hardware implementation of Advanced Encryption Standard , 2006, IEEE Transactions on Computers.

[4]  Israel Koren,et al.  Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard , 2003, IEEE Trans. Computers.

[5]  Ingrid Verbauwhede,et al.  Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors , 2006, IEEE Transactions on Computers.

[6]  Arash Reyhani-Masoleh,et al.  Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[7]  Jean-Jacques Quisquater,et al.  A Differential Fault Attack Technique against SPN Structures, with Application to the AES and KHAZAD , 2003, CHES.

[8]  Ramesh Karri,et al.  Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[9]  Israel Koren,et al.  Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[10]  Israel Koren,et al.  An efficient hardware-based fault diagnosis scheme for AES: performances and cost , 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

[11]  Ramesh Karri,et al.  Low cost concurrent error detection for the advanced encryption standard , 2004 .

[12]  Pierre Dusart,et al.  Differential Fault Analysis on A.E.S , 2003, ACNS.

[13]  M. Anwar Hasan,et al.  Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m) , 2004, IEEE Transactions on Computers.

[14]  Keshab K. Parhi,et al.  High-speed VLSI architectures for the AES algorithm , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.